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06-25-24 08:29 AM |
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| Main - SMW Hacking - wla/dma problems... | New thread | New reply |
| cory21391 |
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 Flurry Level: 37 Posts: 36/260 EXP: 333449 Next: 4804 Since: 03-01-07 From: NC, US Last post: 5188 days Last view: 5188 days |
Well, I've been reading the tutorials at http://vintagedev.tehskeen.com/
and I've gotten to the dma/cgram part, which i understand, but my code doesn't work when i assemble it with wla, just produces a black screen. I understand the tutorials, but maybe i'm overlooking something. I've re-read it like 4 times, but I just can't figure out what could POSSIBLY BE WRONG WITH MY CODE!!! Maybe it's wla or my computer or something in my code I've overlooked. Please help because this is getting annoying (been trying to get it to work for like 5 days) Here's the ENTIRECODE (Oh and when I .INCLUDE an asm or inc file, it doesn't work): ;==================== ;HEADER ;==================== .MEMORYMAP SLOTSIZE $8000 DEFAULTSLOT 0 SLOT 0 $8000 .ENDME .ROMBANKSIZE $8000 .ROMBANKS 8 .SNESHEADER ID "CORY" NAME "SNES Test Program " SLOWROM LOROM CARTRIDGETYPE $00 ROMSIZE $08 SRAMSIZE $00 COUNTRY $01 LICENSEECODE $00 VERSION $00 .ENDSNES .SNESNATIVEVECTOR COP EmptyHandler BRK EmptyHandler ABORT EmptyHandler NMI EmptyHandler IRQ EmptyHandler .ENDNATIVEVECTOR .SNESEMUVECTOR COP EmptyHandler ABORT EmptyHandler NMI EmptyHandler RESET Start IRQBRK EmptyHandler .ENDEMUVECTOR .BANK 0 SLOT 0 .ORG 0 .SECTION "EMPTYVECTORS" SEMIFREE EmptyHandler: rti .ENDS .EMPTYFILL $00 ;==================== ;INITIALIZATION ;==================== .BANK 0 SLOT 0 .ORG 0 .SECTION "InitializeSNESCode" FORCE InitializeSNES: PHK ;set Data Bank = Program Bank PLB LDA #$0000 ;set Direct Page = $0000 TCD ;Transfer Accumulator to Direct Register LDX $1FFD ;we clear all the mem at one point ... STX $4372 ;so save the return address in a place that won't get overwritten LDX $1FFF STX $4374 SEP #$20 ; mem/A = 8 bit REP #$10 LDA #$8F STA $2100 ;turn screen off for now, set brightness to normal LDX #$2101 _Loop00: ;regs $2101-$210C STZ $00,X ;set Sprite,Character,Tile sizes to lowest, and set addresses to $0000 INX CPX #$210D BNE _Loop00 _Loop01: ;regs $210D-$2114 STZ $00,X ;Set all BG scroll values to $0000 STZ $00,X INX CPX #$2115 BNE _Loop01 LDA #$80 ;reg $2115 STA $2115 ; Initialize VRAM transfer mode to word-access, increment by 1 STZ $2116 ;regs $2117-$2117 STZ $2117 ;VRAM address = $0000 ;reg $2118-$2119 ;VRAM write register... don't need to initialize STZ $211A ;clear Mode7 setting LDX #$211B _Loop02: ;regs $211B-$2120 STZ $00,X ;clear out the Mode7 matrix values STZ $00,X INX CPX #$2121 BNE _Loop02 ;reg $2121 - Color address, doesn't need initilaizing ;reg $2122 - Color data, is initialized later LDX #$2123 _Loop03: ;regs $2123-$2133 STZ $00,X ;turn off windows, main screens, sub screens, color addition, INX ;fixed color = $00, no super-impose (external synchronization), CPX #$2134 ;no interlaced mode, normal resolution BNE _Loop03 ;regs $2134-$2136 - multiplication result, no initialization needed ;reg $2137 - software H/V latch, no initialization needed ;reg $2138 - Sprite data read, no initialization needed ;regs $2139-$213A - VRAM data read, no initialization needed ;reg $213B - Color RAM data read, no initialization needed ;regs $213C-$213D - H/V latched data read, no initialization needed STZ $213E ;reg $213E - might not be necesary, but selects PPU master/slave mode ;reg $213F - PPU status flag, no initialization needed ;reg $2140-$2143 - APU communication regs, no initialization required ;reg $2180 - read/write WRAM register, no initialization required ;reg $2181-$2183 - WRAM address, no initialization required ;reg $4016-$4017 - serial JoyPad read registers, no need to initialize STZ $4200 ;reg $4200 - disable timers, NMI,and auto-joyread LDA #$FF STA $4201 ;reg $4201 - programmable I/O write port, initalize to allow reading at in-port ;regs $4202-$4203 - multiplication registers, no initialization required ;regs $4204-$4206 - division registers, no initialization required ;regs $4207-$4208 - Horizontal-IRQ timer setting, since we disabled this, it is OK to not init ;regs $4209-$420A - Vertical-IRQ timer setting, since we disabled this, it is OK to not init STZ $420B ;reg $420B - turn off all general DMA channels STZ $420C ;reg $420C - turn off all H-MA channels STZ $420D ;reg $420D - ROM access time to slow (2.68Mhz) LDA $4210 ;reg $4210 - NMI status, reading resets ;reg $4211 - IRQ status, no need to initialize ;reg $4212 - H/V blank and JoyRead status, no need to initialize ;reg $4213 - programmable I/O inport, no need to initialize ;reg $4214-$4215 - divide results, no need to initialize ;reg $4216-$4217 - multiplication or remainder results, no need to initialize ;regs $4218-$421f - JoyPad read registers, no need to initialize ;regs $4300-$437F ;no need to intialize because DMA was disabled above ;also, we're not sure what all of the registers do, so it is better to leave them at ;their reset state value JSR ClearVRAM ;Reset VRAM JSR ClearPalette ;Reset colors STZ $2102 ;sprites initialized to be off the screen, palette 0, character 0 STZ $2103 LDX #$0080 LDA #$F0 _Loop08: STA $2104 ;set X = 240 STA $2104 ;set Y = 240 STZ $2104 ;set character = $00 STZ $2104 ;set priority=0, no flips DEX BNE _Loop08 LDX #$0020 _Loop09: STZ $2104 ;set size bit=0, x MSB = 0 DEX BNE _Loop09 STZ $2181 ;set WRAM address to $000000 STZ $2182 STZ $2183 LDX #$8008 STX $4300 ;Set DMA mode to fixed source, BYTE to $2180 LDX #wram_fill_byte STX $4302 ;Set source offset LDA #:wram_fill_byte STA $4304 ;Set source bank LDX #$0000 STX $4305 ;Set transfer size to 64k bytes LDA #$01 STA $420B ;Initiate transfer LDA #$01 ;now set the next 64k bytes STA $420B ;Initiate transfer PHK ;make sure Data Bank = Program Bank PLB CLI ;enable interrupts again LDX $4372 ;get our return address... STX $1FFD LDA $4374 STA $1FFF RTL wram_fill_byte: .db $00 ClearVRAM: pha phx php REP #$30 ; mem/A = 8 bit, X/Y = 16 bit SEP #$20 LDA #$80 STA $2115 ;Set VRAM port to word access LDX #$1809 STX $4300 ;Set DMA mode to fixed source, WORD to $2118/9 LDX #$0000 STX $2116 ;Set VRAM port address to $0000 STX $0000 ;Set $00:0000 to $0000 (assumes scratchpad ram) STX $4302 ;Set source address to $xx:0000 LDA #$00 STA $4304 ;Set source bank to $00 LDX #$FFFF STX $4305 ;Set transfer size to 64k-1 bytes LDA #$01 STA $420B ;Initiate transfer STZ $2119 ;clear the last byte of the VRAM plp plx pla RTS ClearPalette: PHX PHP REP #$30 ; mem/A = 8 bit, X/Y = 16 bit SEP #$20 STZ $2121 LDX #$0100 ClearPaletteLoop: STZ $2122 STZ $2122 DEX BNE ClearPaletteLoop PLP PLX RTS .ENDS ;==================== ;MACROS ;==================== ;-------------------- ;INITSNES ;-------------------- .MACRO InitSNES sei clc xce REP #$38 LDX #$1FFF TXS JSL $008000 SEP #$20 .ENDM ;-------------------- ;LOADPALETTE ;-------------------- .MACRO LoadPalette lda #\2 sta $2121 ; Start at START color lda #:\1 ; Using : before the parameter gets its bank. ldx #\1 ; Not using : gets the offset address. ldy #(\3 * 2) ; 2 bytes for every color jsr DMAPalette .ENDM ;-------------------- ;LOADBLOCKTOVRAM ;-------------------- .MACRO LoadBlockToVRAM lda #$80 sta $2115 ldx #\2 ; DEST stx $2116 ; $2116: Word address for accessing VRAM. lda #:\1 ; SRCBANK ldx #\1 ; SRCOFFSET ldy #\3 ; SIZE jsr LoadVRAM .ENDM ;==================== ;ROUTINES ;==================== ;-------------------- ;DMAPALETTE ;-------------------- .BANK 0 .ORG 0 .SECTION "DMAPaletteCode" SEMIFREE DMAPalette: pha phx phb php ; Preserve Registers sep #$20 stx $4302 ; Store data offset into DMA source offset sta $4304 ; Store data bank into DMA source bank sty $4305 ; Store size of data block stz $4300 ; Set DMA Mode (byte, normal increment) lda #$22 ; Set destination register ($2122 - CGRAM Write) sta $4301 lda #$01 ; Initiate DMA transfer sta $420B plp ; Restore registers plb plx pla rts ; return from subroutine .ENDS ;-------------------- ;LOADVRAMCODE ;-------------------- .BANK 0 .ORG 0 .SECTION "LoadVRAMCode" SEMIFREE LoadVRAM: pha phx phy phb php ; Preserve Registers sep #$20 stx $4302 ; Store Data offset into DMA source offset sta $4304 ; Store data Bank into DMA source bank sty $4305 ; Store size of data block lda #$01 sta $4300 ; Set DMA mode (word, normal increment) lda #$18 ; Set the destination register (VRAM write register) sta $4301 lda #$01 ; Initiate DMA transfer (channel 1) sta $420B plp ; restore registers plb ply plx pla rts ; return .ENDS ;==================== ;PROGRAMCODE ;==================== .BANK 0 SLOT 0 .ORG 0 .SECTION "PROGRAMCODE" Start: InitSNES lda #$80 sta $2100 ;turns off screen LoadPalette Palette, $00, $08 ;initiates DMA transfer of palette data LoadBlockToVRAM Tiles, $0000, $0020 ;initiates DMA transfer of tile data lda #$0F sta $2100 ;turns screen on with 100% brightness forever: jmp forever ;loops program forever .ENDS ;==================== ;TILEDATA ;==================== .BANK 1 SLOT 0 .ORG 0 .SECTION "TILEDATA" Tiles: .db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00 .db $FF, $00, $FF, $00, $C3, $3C, $81, $7E, $99, $7E, $99, $7E, $81, $7E, $C3, $3C Palette: .db $00, $7C, $FF, $7F, $00, $7C, $10, $7E .ENDS ____________________ 
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| smkdan |
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 Ninji Level: 36 Posts: 36/238 EXP: 290044 Next: 18066 Since: 05-26-07 Last post: 4122 days Last view: 4071 days |
I don't know if neviksti's code changed since I looked at it, but I noticed a couple things. You don't seem to be (in the section 'PROGRAM CODE')...
-specifing a BG Mode ($2105) -enabling your chosen layers on the main screen ($212C) -setting the tile data address for your selected BGs ($210B for 1/2) -setting the tilemap address for your selected BGs ($2107 for #1) anomie has a really good reference for this at romhacking.net. One thing caught me out before; insert a TAB before your macros or WLA will ignore them without warning. Atleast that's what happened to me. Looks like you need to set up a tilemap too. All the info is in regs.txt. |
| cory21391 |
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Flurry Level: 37 Posts: 37/260 EXP: 333449 Next: 4804 Since: 03-01-07 From: NC, US Last post: 5188 days Last view: 5188 days |
do i need to tab .ENDM too?
and what do you mean "You don't seem to be (in the section 'PROGRAM CODE')..." (do you mean the macros?) and here's my new code (minux the header and init routines): Does the "TileMap" MACRO seem ok? I wrote it myself... ;==================== ;MACROS ;==================== ;-------------------- ;INITSNES ;-------------------- .MACRO InitSNES sei clc xce REP #$38 LDX #$1FFF TXS JSL $008000 SEP #$20 .ENDM ;-------------------- ;LOADPALETTE ;-------------------- .MACRO LoadPalette lda #\2 sta $2121 ; Start at START color lda #:\1 ; Using : before the parameter gets its bank. ldx #\1 ; Not using : gets the offset address. ldy #(\3 * 2) ; 2 bytes for every color jsr DMAPalette .ENDM ;-------------------- ;LOADBLOCKTOVRAM ;-------------------- .MACRO LoadBlockToVRAM lda #$80 sta $2115 ldx #\2 ; DEST stx $2116 ; $2116: Word address for accessing VRAM. lda #:\1 ; SRCBANK ldx #\1 ; SRCOFFSET ldy #\3 ; SIZE jsr LoadVRAM .ENDM ;-------------------- ;LOADTILEMAPENTRY ;-------------------- .MACRO TileMap ldx #\1 ;tilemap entry location ldy #\2 ;high and low bytes of tilemap entry stx $2116 ;sets VRAM access address to tilemap entry location sty $2118 ;writes low and high bytes of tilemap entry .ENDM ;==================== ;ROUTINES ;==================== ;-------------------- ;DMAPALETTE ;-------------------- .BANK 0 .ORG 0 .SECTION "DMAPaletteCode" SEMIFREE DMAPalette: pha phx phb php ; preserve registers sep #$20 stx $4302 ; Store data offset into DMA source offset sta $4304 ; Store data bank into DMA source bank sty $4305 ; Store size of data block stz $4300 ; Set DMA Mode (byte, normal increment) lda #$22 ; Set destination register ($2122 - CGRAM Write) sta $4301 lda #$01 ; Initiate DMA transfer sta $420B plp ; Restore registers plb plx pla rts ; return from subroutine .ENDS ;-------------------- ;LOADVRAMCODE ;-------------------- .BANK 0 .ORG 0 .SECTION "LoadVRAMCode" SEMIFREE LoadVRAM: pha phx phy phb php ; Preserve Registers sep #$20 stx $4302 ; Store Data offset into DMA source offset sta $4304 ; Store data Bank into DMA source bank sty $4305 ; Store size of data block lda #$01 sta $4300 ; Set DMA mode (word, normal increment) lda #$18 ; Set the destination register (VRAM write register) sta $4301 lda #$01 ; Initiate DMA transfer (channel 1) sta $420B plp ; restore registers plb ply plx pla rts ; return .ENDS ;==================== ;PROGRAMCODE ;==================== .BANK 0 SLOT 0 .ORG 0 .SECTION "PROGRAMCODE" Start: InitSNES lda #$80 sta $2100 ;turns off screen LoadPalette Palette1, $00, $08 ;initiates DMA transfer of palette data LoadBlockToVRAM Tiles1, $0000, $0030 ;initiates DMA transfer of tile data stz $2105 ;sets all BGs to 8x8 tile size, and sets screen mode to mode 0 lda #$04 sta $2107 ;sets BG1 tilemap location to $0400 in VRAM, with 32x32 screensize stz $210B ;sets BG1 character location to $0000 in VRAM lda #$01 sta $212C ;enables BG1 TileMap $0400, $0001 ;stores tile 1 to tilemap entry 0 TileMap $0401, $0002 ;stores tile 2 to tilemap entry 1 lda #$FF sta $210E sta $210E ;something about Vertical Scroll (register $210E is BG1 Vertical Scroll) lda #$0F sta $2100 ;turns screen on with 100% brightness forever: jmp forever ;loops program forever .ENDS ;==================== ;TILEDATA ;==================== .BANK 1 SLOT 0 .ORG 0 .SECTION "TILEDATA" Tiles1: .db $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00, $FF, $00 .db $FF, $00, $FF, $00, $C3, $3C, $81, $7E, $99, $7E, $99, $7E, $81, $7E, $C3, $3C .db $FF, $00, $FF, $00, $DB, $24, $FF, $00, $BD, $42, $81, $7E, $FF, $00, $FF, $00 Palette1: .db $00, $7C, $FF, $7F, $00, $7C, $10, $7E .ENDS ____________________
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