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| Acmlm's Board - I3 Archive - ROM Hacking - SNES HiROM Memory Mapping questions |
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Sukasa Birdo Not quite as active as before. Xkeeper supporter Xk > ||bass I IP Banned myself! Twice!                    Since: 11-17-05 From: Somewhere over there Last post: 6290 days Last view: 6289 days |
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| I have a couple of questions on the HiROM Memory Model.
1) The readout I have lists both Mode 21 SRAM and Mode 20 SRAM. Can I use bothe, or just the mode 21 SRAM? 2) How do the banks $00 to $3F, $40 to $5F, $80 to $BF, and $C0 - $FF correlate to the .smc file output by a compiler such as WLA-65816 and WLALINK? I'm wondering so that I don't mess up my ROM's pointers and where everything goes while writing a PD ROM. 3) What are the "RESERVED" Addresses for, and Can/How Can I use them 4) There's a PPU 2 listed on this sheet at addresses $4200 to $5FFF (along with the DMA regs, etc.), as well as the standard PPU 1 that is at addresses $2000 to $2FFF. Has anyone else heard of it? |
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MathOnNapkins  1100  In SPC700 HELL  Since: 11-18-05 Last post: 6289 days Last view: 6289 days |
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| Well I don't know specifically all the details, but considering emulators work (more or less), you should try experimenting with a rom and viewing it in a debugger to see what gets mapped to what.
1) What are you even talking about? Lo-Rom is mode 20, Hi-Rom is mode 21. You can't mix them. Besides, the memory map is the same. Your question makes no sense. 2) Can't help you with WLADX. Can't you just declare what bank you want the code to go in in WLADX? 3) I would assume RESERVED means inaccessible to the programmer unless otherwise mapped in (Super FX or other chips, Xband, specially wired Static RAM, etc) 4) PPU2, yes I've heard of it, what's your point? Also, this question is largely irrelevant to this forum. Why don't you post your SNES related questions in the romhacking forum, as they are more likely to get answers there? You're probably just bothering the forumgoers here. |
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Sukasa Birdo Not quite as active as before. Xkeeper supporter Xk > ||bass I IP Banned myself! Twice! Since: 11-17-05 From: Somewhere over there Last post: 6290 days Last view: 6289 days |
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| OK, I'll use that forum next time. Oh, and I asked about the two modes things becuase I didn't understand why the Mode 20 SRAM would have been listed in the HiROM memory map as well as the regular LoROM one. And according to the two memory models I have, the mapping aren't the same... sorry.
And I'll look up the PPU2, since I was interested in seeing about whether it existed, and if so, possibly using it somehow. |
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MathOnNapkins 1100 In SPC700 HELL Since: 11-18-05 Last post: 6289 days Last view: 6289 days |
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| If you use DMA you have to use PPU2. You know, the $42XX registers that set up the transfers? The difference between PPU2 and PPU1 (as I recall) is that they have different bus widths and are possibly connected to different buses (A bus vs. B bus) of the main processor. I'd have to dig through the official documentation to know for sure. All in all, I just call both of them the "PPU", though for some applications you have to consider them separately. | |||
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Sukasa Birdo Not quite as active as before. Xkeeper supporter Xk > ||bass I IP Banned myself! Twice! Since: 11-17-05 From: Somewhere over there Last post: 6290 days Last view: 6289 days |
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| Af... I need to revise my understanding of DMA... I understood that DMA hardwaired to $21xx, which is PPU1. I'll look at PPU2, if it works with 16-bit register widths that'd be great. I'll go looking for that documentation. | |||
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MathOnNapkins 1100 In SPC700 HELL Since: 11-18-05 Last post: 6289 days Last view: 6289 days |
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| Pretty sure you can use 16 bit registers on either PPU, but what I meant was what addresses in memory each PPU had access to. i.e. 24 bit addressing versus 8-bit addressing. | |||
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Sukasa Birdo Not quite as active as before. Xkeeper supporter Xk > ||bass I IP Banned myself! Twice! Since: 11-17-05 From: Somewhere over there Last post: 6290 days Last view: 6289 days |
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| What I meant was that the way I understood your post, the PPU1 had to be written to twice, once for each byte in the Accumulator, whereas I understood you as saying that PPU2 can have one write of both bytes at once.
Offtopic: I like the new description of this forum, including the little sidenote. |
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